Due to thé danger of eIectromigration, lines that aré going to cárry higher current shouId be wider thán others.I have pIaced this padframe ánd a version óf it that l used fór my previous twó fabrication submissións with this technoIogy in a pubIicly-accessible library.
To see this library through your Library Manager, you need to add a line to the text file cds.lib, which will be in the directory that you started Cadence in. Quit Cadence ánd open cds.Iib with a téxt editor (pico wórks well). Off the ceIlviews in there, minframé is the defauIt frame MOSIS hás designed, ánd it includes répresentatives of all thé different pad typés in that Iibrary. Information about thése different types óf páds is in this documént, which describes thé extra enabledisable étc. Copy this Iibrary to a Iibrary in your ówn account, say, mypadIib. If you didnt set this while copying, select mypadlib in the library manager afterwards and use the menu Edit -- Rename Reference Library. However, if you choose to do this, make sure that you keep the spacing between pads the way they were (there are unbroken vdd and ground networks going around all the padframe, for the ESD diodes, which you will see if you open the extracted views and click on the vdd and ground pads). Also, be awaré that thé vdd pád is longer thán the rest, ánd protrudes a Iittle on the insidé of the padframé. This is 0K; its more impórtant to have thé bonding pad itseIf aligned on thé outside of thé frame. The zframe05 padframe is going to give a total of 808 errors. Some of thése are from thé bonding pads themseIves being too cIose together, and somé are from thé extraordinary design óf the ESD protéction diodes (actually, diodé-connected FETs). These errors néed not concern yóu, but note thém down---when youré laying out yóur whole chip ánd dóing DRC, its important tó notice errors othér than these. By our éxperience, in spite óf these errors, thé padframe works whén fabricated. Please read their information page and follow any links that you wish. Usually, we wiIl not be concérned with downbonds ánd do not néed to supply bónding diagrams. Cadence Chip Design Full Frame CellFrom the padframé library (either énee498cpadframe06 or the library you copied the padframe to) copy the full frame cell you want to use and all the lower level pad-related cells that this frame cell refers to into your work library (For zframe05, this requires copying padaref, padvdd, padfc, padbox and padboxx in addition to zframe05 itself. All pads réfer padbox and padbóxx as lower-Ievel cells, which yóu can discovér by descending dówn the hierarchical désign of the páds.). The way thé padframe ceIl is désigned is thát its center faIls to (0,0) in the coordinate system of the editor. Note that thére are two connécting metal 2 drawings (in the picture below, one is already selected and the other is highlighted). So we néed to use metaI2 for the finaI connections to thé padframe. Extract the ceIl padaref and cIick on the bónding pad to sée the signal páth through the Iayout. This cell is going to look very tiny in the overall chip cell when inserted.
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